ASIC Digital Design, Sr Staff Engineer-18490

Your configuration software will determine whether DDR PHY IP integrates cleanly into customer designs or creates weeks of bring-up delays

The firmware you write will run on millions of chips across data center, mobile, automotive, and AI applications

Your debugging work will directly reduce time to first silicon success for customers building next-generation systems

The automation flows you build will accelerate how quickly the team can validate new features and release to customers

Your input on design decisions will shape how configurable and de-buggable future PHY generations are from day one

The quality of your code will affect how reliably high-speed memory interfaces train and operate in production systems

Your collaboration with design and verification will close the loop between what the RTL does and what customers can use

Bachelor’s degree in electrical engineering, Computer Engineering, or equivalent practical experience

5+ years of hands-on experience in ASIC design, verification, or firmware development, ideally involving configuration or bring-up work

Strong C programming skills with experience writing firmware or embedded software for hardware systems

Solid understanding of data structures, algorithms, and software design principles applied to hardware configuration problems

Proficiency in scripting languages like Python or Perl for automation, code generation, or build flows

Proven debugging skills across multiple layers, firmware, RTL, registers, and silicon behavior

Experience with high-speed interface protocols such as DDR, LPDDR, or other memory standards is a strong plus

You can read RTL well enough to understand what a configuration register does, not just what the spec says it should do

You write code that other engineers can debug six months later without needing you in the room

When a bring-up fails, you methodically work through failure, checking assumptions and isolating variables instead of guessing

You communicate clearly with design engineers who think in Verilog and verification engineers who think in test benches, translating between their worlds and yours

You push back when a new feature is underspecified from a software perspective, and you do it early enough to matter

You are comfortable working across time zones with a global team, and you document your work in a way that makes asynchronous collaboration work

You will join the DDR PHY IP team within Synopsys' Silicon Design & Verification business. This team builds the physical layer IP that enables high-speed memory interfaces in chips across every major market, from mobile to data center to automotive. The group is responsible for the full stack: analog design, digital design, verification, and the configuration software that ties it all together. Your work on PHYINIT will sit at the center of that stack, directly enabling how customers integrate and use the IP.