ASIC Digital Design, Principal Engineer

Lead a team of verification engineers through full IP verification cycles, from test plan definition through coverage closure and signoff

Build and evolve SystemVerilog/UVM verification environments for DesignWare synthesizable IP cores, ensuring they scale across multiple product generations

Define test plans that cover corner cases, protocol compliance, and system-level interactions, then review and guide implementation across the team

Write and debug complex testbenches, checkers, and assertions for serial interface protocols and memory controllers, including DDR and LPDDR where applicable

Extract, analyze, and drive functional coverage and code coverage metrics to closure, identifying gaps and adjusting strategy in real time

Collaborate directly with RTL designers, digital architects, and circuit teams to align verification scope with design intent and catch issues early

Manage regression infrastructure and work with the infra team to keep verification cycles efficient and reliable

Deliver verification signoff on IP cores that ship in millions of devices, ensuring they work correctly the first time in silicon

Raise the bar for verification quality across the DesignWare team by mentoring engineers and evolving testbench architecture and methodology

Catch critical bugs before tapeout that would otherwise cost months of schedule and customer trust

Influence IP architecture decisions by surfacing verification insights early, when design changes are still cheap

Help shape how the team adopts AI-assisted verification flows, improving efficiency without sacrificing rigor

Contribute to Synopsys' leadership in IP by ensuring that what we deliver is not just feature-complete but robustly verified

Build verification environments and strategies that other teams will reuse and learn from, multiplying your impact across the organization

Bachelor's or Master's in Electrical Engineering or Electronics and Communication Engineering with 8+ years of hands-on verification experience

Proven track record leading verification teams through IP project delivery, including planning, execution, and signoff

Strong experience developing SystemVerilog/UVM testbenches from scratch and evolving them as designs grow

Deep expertise writing test plans, implementing checkers, and building assertions that catch real bugs

Proficiency extracting and interpreting functional coverage and code coverage, and using those metrics to drive verification closure

Experience verifying serial interface protocols and working through IP design and verification processes, knowledge of DDR or LPDDR protocols is a strong plus

Demonstrated ability to own end-to-end verification deliverables, including metric closure and formal review signoff, experience with AI-assisted verification tools is a plus

You can explain a coverage hole to an architect in two sentences and walk out with a plan to close it

You debug by hypothesis, not by adding print statements until something makes sense

When a testbench is too slow or too brittle, you refactor it instead of working around it

You give feedback that makes engineers better, not just feedback that makes the code pass

You work across time zones and teams without losing context or creating confusion downstream

You know when to push back on a design decision and when to adjust the verification plan to match reality

You will join Synopsys' DesignWare IP Verification R&D team in Bangalore, working with a global group of experienced verification engineers who are responsible for ensuring the quality and reliability of IP cores that power semiconductors across the industry. This team collaborates closely with RTL designers, architects, and infrastructure engineers to deliver robust, production-ready IP.