ASIC Digital Design, Architect

Your architectural decisions will define the performance, power, and area of SerDes IP used in high-volume networking and storage products worldwide

The design flows and methodologies you establish will set the standard for how the team handles CDC, DFT, and low-power design across future product generations

Your collaboration with verification will reduce tapeout risk and catch critical issues before they reach silicon

The testplans and coverage strategies you help create will directly improve functional quality and reduce post-silicon debug cycles

Your mentorship will accelerate the growth of junior engineers and raise the technical bar across the team

The specifications you write will become the foundation for cross-functional alignment between digital, analog, verification, and implementation teams

Your work will enable customers to deliver faster, lower-power, more reliable connectivity in everything from data centers to consumer devices

Master's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience

10+ years of hands-on digital ASIC design experience, with significant work in high-speed or mixed-signal environments

Strong proficiency in Verilog or VHDL for RTL design and gate-level simulation

Deep understanding of clock domain crossing design, analysis, and verification methodologies

Hands-on experience with synthesis tools and techniques, including timing closure and power optimization

Solid knowledge of DFT methodologies including scan insertion, ATPG, and boundary scan

Experience working closely with verification teams on testplan creation, coverage closure, and failure analysis. Familiarity with high-speed digital interfaces such as Ethernet, PCIe, SATA, or USB is a strong plus.

You can look at a block diagram and immediately spot the async crossing that is going to cause problems three months from now

You write RTL with synthesis in mind, not as an afterthought, and you know how to balance design intent with tool limitations

You are comfortable sitting with an analog designer to hash out an interface spec, then turning around and explaining the same thing to a verification engineer in a way that makes sense for testbench architecture

You do not wait for perfect documentation. You ask the right questions, fill in the gaps, and move forward without creating downstream confusion

You have strong opinions about code quality, coverage metrics, and design methodology, and you are willing to push back when something does not make sense

You can explain a complex timing or power tradeoff to a senior leader in two sentences without losing the technical nuance

You will join a highly experienced mixed-signal design team responsible for delivering industry-leading SerDes IP for Backplane Ethernet, PCIe, SATA, and USB standards. This team works across the full design cycle, from early specification development through silicon validation and customer support. Your recruiter will share more about the team structure, current product roadmap, and collaboration model during the interview process.