ASIC Design Verification Engineer, TPU Compute

Responsibilities

• Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM).
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
• - Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. - Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). - Identify and write all types of coverage measures for stimulus and corner-cases. - Debug tests with design engineers to deliver functionally correct design blocks. - Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications:

Preferred qualifications: