ASIC Design Team Lead

• The successful candidate is a recognized expert who designs, researches, and develops highly advanced applications supporting Arcfield’s secure processing projects.
• As such, you will lead a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components.
• You will finish developing, enhancing, and debugging the VHDL/Verifog for the chip.
• This includes verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus.
• You will perform clock domain crossing (CDC) and reset domain crossing (RDC) verification.
• You will perform Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design. You will develop and port the RTL to an FPGA prototyping board.
• You will perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS).
• You will also help the design team run static timing analysis and power analysis after the CTS and place and route. Packaging and an evaluation board for the physical chip must also be performed.
• As Design Lead you will supervise the development and maintenance of technical procedures, documentation, and manuals and lead the Design team to compile and analyze operational data and direct tests to establish standards for new designs or modifications to existing equipment, systems, or processes.
• You will also coordinate and consult with research engineers or scientists and customer representatives to resolve design problems.
• Bachelor degree in Hardware or Electrical Engineering (EE) with 12-15 years of experience or a Master's degree in Hardware or Electrical Engineering (EE) with 10-13 years of experience or a Ph.D in Hardware or Electrical Engineering (EE) with 10+ years of experience.
• Must be able to obtain and maintain a Secret clearance
• Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
• Minimum 3 years experience using Cadence Virtuoso
• Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
• Minimum 3 years experience using ModelSim/QuestaSim

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