Analog Design, Staff Engineer

Design and develop analog sub-blocks for multi-Gbps NRZ and PAM4 SerDes IP, including equalizers, samplers, drivers, VCOs, PLLs, DLLs, ADCs, DACs, and serializers/deserializers

Review SerDes standards and translate them into block-level specifications that balance power, area, and performance across the latest FinFET process nodes

Identify and refine circuit architectures, evaluating multiple topologies and making design decisions that account for layout constraints, process variation, and reliability

Oversee physical layout implementation, working closely with layout engineers to minimize parasitics, manage device stress, and ensure robust matching and ESD protection

Develop simulation strategies using SPICE simulators, Verilog-A behavioral models, and scripting (TCL, Perl, Python, MATLAB) to verify circuit performance across corners and conditions

Present simulation data and design reviews to peers and customers, documenting design features, test plans, and tradeoffs

Consult on post-silicon characterization and propose design updates based on electrical test results

Your circuit architectures will directly shape the power, area, and performance of SerDes IP that ships in high-volume semiconductor products

The design strategies and verification methods you develop will become reference flows for the analog team, raising the bar for quality and efficiency

Your layout oversight will reduce post-silicon surprises, cutting time to market and improving first-pass silicon success rates

The simulation data and documentation you produce will enable faster customer adoption and smoother integration of SerDes IP into SoC designs

Your collaboration with digital designers and software teams will strengthen cross-functional design practices and improve overall IP robustness

The design-for-reliability and ESD techniques you implement will extend product lifetime and reduce field failures

Your contributions to post-silicon debug will close the loop between design intent and measured performance, driving continuous improvement

Bachelor's degree with 6+ years of relevant experience or Master's degree with 4+ years of relevant experience in Electrical Engineering, Computer Engineering, or a related field

Deep transistor-level circuit design experience with strong CMOS design fundamentals and hands-on work in advanced process nodes

Detailed design experience with at least one SerDes sub-circuit (receive equalizers, samplers, voltage/current-mode drivers, serializers, deserializers, VCO, phase mixer, DLL, PLL, bandgap reference, ADC, DAC) and familiarity with several others

Proficiency with SPICE simulators and simulation methods, including corner analysis, Monte Carlo, and aging simulations

Working knowledge of Verilog-A for analog behavioral modeling, simulation control, and data capture

Experience with schematic entry, physical layout, and design verification tools, hands-on layout experience with high-speed circuits is a plus

Familiarity with scripting languages such as TCL, Perl, Python, C, or MATLAB for automation and data analysis is desired

You can look at a block spec and quickly sketch two or three circuit topologies, then articulate the tradeoffs between them in a design review without needing slides

You treat layout as part of the design, not an afterthought, and you know how to work with layout engineers to get matching, parasitics, and floorplanning right the first time

You are comfortable presenting simulation data to customers and peers, defending your design choices, and adjusting your approach when the data tells you to

You know the difference between a simulation that gives you confidence and one that just checks a box, and you design your verification strategy accordingly

You can move between deep circuit-level work and system-level discussions with digital designers, understanding how your block fits into the larger SerDes architecture

You document your work clearly, not because someone asked you to, but because you know the next person (or future you) will need to understand what you built and why

You will join a growing analog and mixed-signal R&D team focused on high-speed SerDes IP development in the latest FinFET process nodes. The team works cross-functionally with digital designers, software engineers, and a dedicated CAD team that supports custom in-house tools alongside a full suite of industry-standard IC design tools. Your recruiter will share more about the team structure and mission during the interview process.